The memory matrix architecture most widely utilized in the construction of semiconductor integrated, non-volatile memory devices is the NOR type. In this type of architecture, memory cells belonging to one row have their gate terminals in common, while memory cells belonging to one column have their drain terminals in common. The source terminals are, on the other hand, shared by all the cells of one sector. A portion of a NOR matrix, reprinted from U.S. Pat. No. 6,515,911, the entirety of which is incorporated by reference herein, is shown in FIG. 1.
Each memory location is identified by a given row and given column and found at the intersection thereof. Each memory cell comprises a floating-gate transistor which has drain and source conduction terminals. As known in the art, the source, drain and gate terminals are biased accordingly to perform read, program and erase operations.
A prerequisite of non-volatile memories of the flash EEPROM type is that the information stored therein should be erased by groups or packages of bits. The erase operation is the only operation that involves biasing of the source terminal, and since all the cells have this terminal in common, they can be written into and read from in an independent manner but must be erased simultaneously.
Particularly with flash memories, the erase operation is performed by sectors, in the sense that all the cells that run to the same source line must be erased simultaneously. Within a non-volatile memory matrix, the sectors can be organized either into rows or columns. In a row type of organization, the size of a sector is given by the number of rows that it contains. The architecture of the storage device is designed to fit the number and size of the sectors in order to optimize the circuit area consumption, as well as the device performance and reliability.
A single bit line is not shared by all of the sectors because of a problem known as “drain stress.” Therefore, each sector is arranged to include a specific group of columns referred to as the “local bit lines.” Local bit lines are individually connected, via a pass transistor, to a main metallization connection referred to as the “main bit line.” Each sector is assigned a local group of pass transistors which are only turned “on” in the addressed sector, so that the cells of the other sectors need not be affected by drain stress.
Shown schematically in FIG. 2, also reprinted from the '911 Patent, is a conventional architecture for a non-volatile memory matrix wherein the sectors are organized into rows. The rows of the memory matrix are physically in the form of polysilicon strips interconnecting all the gate terminals of the cells in one row. The architecture includes a plurality of sectors each having an associated row decoder. A global column decoder is also provided. This architecture consumes a lot of circuit space because it entails the provision of a row decoder for each sector, and of local column decoders to avoid the drain stress phenomenon.
Another prior art architecture shown in FIG. 3, also reprinted from the '911 Patent, organizes the non-volatile memory matrix into columns. In this case, the rows are shared in common by all sectors, and the sector size is determined by the number of columns. This architecture keeps the parasitic capacitance of each bit line relatively low, which is beneficial to the circuit portion involved in reading the memory contents. In addition, row decoding is shared by several sectors, which affords savings in circuit space. While being advantageous in several ways, this architecture has a drawback in that each time when a cell is addressed, all the other cells in the same row also are biased and affected by the so-called “gate stress.”
In view of the shortcomings of these prior art architectures, the '911 Patent proposes embodiments of hierarchical row decode. In one described embodiment, a circuit device is provided capable of carrying out a hierarchical form of row decoding for semiconductor memory devices of the non-volatile type having a matrix of memory cells with sectors organized into columns. Each sector has a specific group of local word lines individually connected to a main word line running through all of the sectors which have rows in common. The '911 Patent describes a three transistor structure for carrying out the hierarchical row decoding.
The word line driver design for the row decoders of these NOR architectures has become increasingly more important since the periphery transistors of the driver design cannot shrink proportionately with reductions in the size of the cell dimensions, as the driver transistors must be able to sustain the bias conditions of legacy generations. Therefore, as cell sizes reduce, the word line driver occupies a greater amount of the overall circuit layout area. While there are advantages to hierarchical row decoding schemes such as those proposed in the '911 Patent, these schemes consume valuable space. Therefore, improved word line driver designs are desired.